Microelectronic circuits have shrunk well into the sub-micron range, and their size continues to shrink even smaller with each passing generation of technology. As this miniaturization continues, each step of the manufacturing process becomes even more critical to assure as great a yield of defect-free devices as possible. Even the most initial and seemingly insignificant steps of the manufacturing process are important in assuring commercially feasible device yields.
One area that has grown in importance as device sizes have shrunk is the deposition chamber that is used to deposit the various layers that make up a microelectronics device. The industry has long since learned the importance of conditioning or seasoning the chamber prior to depositing a dielectric layer that is intended to isolate the various layers within the device from each other. The chamber is typically seasoned or conditioned by depositing a conditioning layer on the walls of the deposition chamber. It has been found that conditioning the deposition chamber provides for a more uniform wafer to wafer thickness control, as well as within wafer thickness uniformity, which is important in maintaining high device quality yields between individual wafers and wafer lots.
While design configurations vary from tool to tool, a deposition chamber will typically consist of six deposition stations within a main chamber. The wafer is inserted and is moved from station to station where sequential deposition takes place until the wafer has passed through all six stations. A shower head, from which deposition gases are dispensed, is located over each station. In the case of dielectric deposition, tetra-ortho silicate (TEOS) gas and oxygen gas are flowed under plasma conditions to form the dielectric layer. The TEOS is brought from a supply tank via a supply line as a liquid. Prior to being dispensed from a deposition shower head, however, the liquid TEOS is heated to turn it into a gas, which is then mixed with the oxygen and expelled from the shower head under plasma conditions to form the dielectric.
While every step is taken to reduce or eliminate the possibility of contaminate particles, contamination still occurs within the deposition chamber despite the best of efforts. Thus, to assure that contamination is not occurring within the deposition tool itself, the typical and present industry standard is to measure for particles on the wafer having a size of at least around 0.2 microns or greater. Until recently, this has seemed to be an adequate practice, but as devices sizes have continued to shrink deep into the sub-micron range, it has been noticed that defects are occurring in the devices at subsequent deposition steps, even though acceptable particle defectivity measurements are being obtained. It is believed that one reason for this is that as device sizes shrink, the metal density increases and any particle has a greater chance of causing a failure on the wafer. Thus, it is apparent that present pre-conditioning processes are not adequate to assure minimization of wafer to wafer particle defects.
Accordingly, what is needed in the art is a pre-conditioning process that will reduce particle defects in a wafer and can be implemented without substantial change in equipment or existing processing steps.